Materials &

“It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.”

—Gordon Moore, 1965

Can the integration of unconventional materials enhance conventional silicon circuits and continue the progress traditionally associated with scaling?

Phase II – Differentiated Access

Photonics in the Package for Extreme Scalability (PIPES)

The Photonics in the Package for Extreme Scalability (PIPES) program seeks to develop high-bandwidth optical signaling technologies for digital microelectronics. By intimately integrating photonic and electronic components at the chip-package level, PIPES will overcome the physics-limited bottleneck of electrical data transfer between computing components. The development of efficient, high bandwidth package-level photonic signaling is anticipated to impact a host of applications, including machine learning, large scale emulation, high performance computing, advanced sensors and wireless interfaces. PIPES will aid commercial advances through technology investment, aligning these commercial outcomes with national security impact.

Technologies For Mixed-Mode Ultra Scaled Integrated Circuits (T-MUSIC)

The Technologies for Mixed-Mode Ultra Scaled Integrated Circuits (T-MUSIC) program seeks to disrupt RF mixed-mode technologies. T-MUSIC will develop integrated, ultra-broadband, mixed-mode electronics with embedded advanced digital CMOS electronics in a U.S. domestic foundry fabrication platform. The resulting highly integrated digital processing with intelligence on a chip will provide differentiated capabilities for DoD systems. It will enable next generation RF mixed-mode interfaces with an unprecedented combination of wide spectral coverage, high resolution, large dynamic range, and high information processing bandwidth. T-MUSIC will provide the foundation for enduring U.S. leadership in mixed-mode electronics technology for DoD and commercial 5G/6G wireless applications.

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Three Dimensional Monolithic System-on-a-Chip (3DSoC)

The overall goal of the Three Dimensional Monolithic System-on-a-Chip (3DSoC) program is to develop 3D monolithic technology that will enable > 50X improvement in System-on-a-Chip (SoC) digital performance at power. 3DSoC aims to drive research in process, design tools, and new compute architectures for future designs while utilizing U.S. fabrication capabilities. 

Foundations Required for Novel Compute (FRANC)

The goal of the Foundations Required for Novel Compute (FRANC) program is to define the foundations required for assessing and establishing the proof of principle for beyond von Neumann compute architectures. FRANC will seek to demonstrate prototypes that quantify the benefits of such new computing architectures.

Foundational ERI

Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS)

To enhance overall system flexibility and reduce design time for next-generation products, the Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS) program seeks to establish a new paradigm in IP reuse. CHIPS envisions an ecosystem of discrete modular, reusable IP blocks that can be assembled into a system using existing and emerging integration technologies. Modularity and reusability of IP blocks will require electrical and physical interface standards to be widely adopted by the community supporting the CHIPS ecosystem. Therefore, the program will develop the design tools and integration standards required to demonstrate modular integrated circuit (IC) designs that leverage the best of DoD and commercial designs and technologies.